As a method for dividing a semiconductor wafer, there is generally adopted a method in which grooves are formed in the wafer by dicing or scribe lines are formed by scribing, and the wafer is then divided by breaking with the aforementioned grooves or the scribe lines as starting points and along the scribe lines. Dicing is a method for forming dicing grooves in the wafer by the relative movement between a rotary blade of a dicer (dicing saw) and the wafer. Scribing is a method for forming scribe lines in the wafer by the relative movement between a sharp-edged blade of a scriber and the wafer. Breaking is a method for pressing the wafer with a press blade or a press roller to thereby divide the wafer by three-point bending.
In a semiconductor wafer using a substrate made of a high-hardness material (e.g. sapphire, GaN, etc.), it is difficult to divide the wafer by breaking only if shallow dicing grooves or scribe lines are formed in the wafer. It is therefore necessary to do breaking after ingenuity such as dicing the wafer deep, scribing the wafer with the substrate thinned on a large scale, or the like, is added. For example, the following methods are known as methods in which a wafer having a gallium-nitride-based compound semiconductor laminated onto the surface of a sapphire substrate is divided into chips.
(1) A method disclosed in Japanese Patent No. 2765644 includes the following steps:
    1) the dicing step of cutting grooves deeper than the thickness of the gallium-nitride-based compound semiconductor layer by a dicer;    2) the grinding step of thinning the sapphire substrate by grinding;    3) the scribing step of forming scribe lines in the sapphire substrate with a scriber along the grooves formed in the dicing step; and    4) the dividing step of dividing the wafer into chips after the scribing step.(2) A method disclosed in Japanese Patent No. 2914014 includes the following steps:    1) the first step of thinning the sapphire substrate by grinding;    2) the second step of etching a p-type layer (gallium-nitride-based compound semiconductor) up to an n-type layer to thereby expose the plane of the n-type layer;    3) the third step of etching or dicing the plane of the n-type layer to thereby expose the plane of the sapphire substrate; and    4) the fourth step of dicing or scribing the thinned sapphire substrate, and cutting off the wafer in the plane of the sapphire substrate exposed in the third step.(3) A method disclosed in Japanese Patent No. 2780618 includes the following steps:    1) the step of forming first split grooves linearly into the shape of desired chips by etching on the side of the gallium-nitride-based compound semiconductor layer, while forming a plane in a part of the first split grooves so that electrodes can be formed in the plane;    2) the step of forming second split grooves (preferably scribe lines) in the positions corresponding to the first split grooves on the side of the sapphire substrate of the wafer so that the line width of the second split grooves is narrower than the line width of the first split grooves; and    3) the step of dividing the wafer into chips along the first split grooves and the second split grooves.(4) A method disclosed in Japanese Patent No. 2861991 includes the following steps:    1) the step of forming (by etching) first split grooves linearly into the shape of desired chips on the side of the gallium-nitride-based compound semiconductor layer of the wafer, while forming the first split grooves to reach a depth to an extent that the gallium-nitride-based compound semiconductor layer is penetrated and a part of the sapphire substrate is removed;    2) the step of forming second split grooves (preferably scribe lines) in the positions corresponding to the first split grooves on the side of the sapphire substrate of the wafer so that the line width of the second split grooves is narrower than the line width of the first split grooves; and    3) the step of dividing the wafer into chips along the first split grooves and the second split grooves.
In the methods using dicing and scribing together as in the aforementioned (1) and (2), first, there is a problem that cracking or chipping is apt to occur in the substrate and the semiconductor layer at the time of dicing so that the yield is not very high. In addition, it is necessary to form a large number of dicing grooves and a large number of scribe lines in the wafer. In the present circumstances, those lines have to be formed one by one. Thus, the machining time is so long that the efficiency deteriorates. Further, a rotary blade for dicing is expensive and does not have a very long lifetime.
Further, in the method in which grooves are formed by dicing on the semiconductor layer formation side so as to reach the substrate, and scribe lines are formed in the bottoms of the grooves by a scriber as in the aforementioned (1), the groove width of the grooves has to be made so large that a scribing blade enters the grooves.
On the other hand, in the methods using etching and scribing together as in the aforementioned (3) and (4), first, there is a fear that etching causes damage to the semiconductor layer. Japanese Patent No. 2780618 as in the aforementioned (3) says “Etching is the least efficient way to cause damage to the surface and side faces of the nitride semiconductor” and takes, for instance, dry etching such as reactive ion etching, ion milling, converging beam etching, ECR etching, etc., and wet etching using mixed acid of sulfuric acid and phosphoric acid. Such etching can indeed form a plurality of or a large number of grooves simultaneously, but the machining time is not short at all, so that the efficiency is poor. Further, equipment for etching, particularly equipment for dry etching is so expensive that the machining cost increases.
Further, the reason why the line width of the first split grooves on the semiconductor layer formation side is made larger than the line width of the second split grooves on the sapphire substrate side as in the aforementioned (3) and (4) is to prevent any cutting line generated in the second split grooves from reaching the semiconductor layer even if the line runs obliquely. Accordingly, in embodiments of the same applications, the line width of the first split grooves is made wide to be 80 μm. When the groove width of the grooves formed thus on the semiconductor layer formation side is made wide, there is a problem that the area of the semiconductor layer in each semiconductor chip divided is reduced so that the luminance becomes low. In addition, when the area is prevented from being reduced, there is a problem that the number of semiconductor chips yielded is reduced.